The present invention relates, in general, to data storage elements, and more particularly, to nonvolatile memory units.
A ferroelectric random access memory (FERAM) is generally considered superior to other types of nonvolatile memory in terms of data transfer rate, fatigue characteristics, operating voltage, etc. Two predominant FERAM configurations are a two transistor, two ferroelectric capacitor per bit (2T/2C) configuration and a one transistor, one ferroelectric capacitor per bit (1T/1C) configuration. Because of its small size, the 1T/1C configuration is preferred in high packing density and low power applications, such as portable computers, personal communications, smart cards, and radio frequency identification tags.
In a memory cell with a 1T/1C configuration, a ferroelectric memory capacitor stores a logic state representing the data stored in the memory cell. When reading data from the memory cell, an extraction voltage is applied to the ferroelectric memory capacitor to extract the polarization charge from the memory capacitor. The extracted polarization charge is transmitted to a parasitic bit line capacitor. The voltage across the parasitic bit line capacitor is compared with a reference voltage to determine whether the data read from the memory cell is a logic high or logic low.
The reference voltage is typically provided by a ferroelectric reference capacitor which has a larger capacitance than that of the memory capacitor. The reference capacitor is polarized in a logic low state. When reading data from the memory cell, the extraction voltage is applied to both the memory capacitor and the reference capacitor. A reference charge is extracted from the reference capacitor and transmitted to a parasitic reference bit line capacitor. When the amount of charge extracted from the reference capacitor is larger than the amount of charge extracted from the memory capacitor, the memory cell is storing a logic low state. When the amount of charge extracted from the reference capacitor is smaller than the charge extracted from the memory capacitor, memory cell is storing a logic high state. Thus, reading data from the memory cell includes comparing the voltage across the bit line capacitor with the voltage across the reference bit line capacitor.
The data is correctly read from the memory cell only if the capacitance of the reference capacitor is larger than the capacitance of the memory capacitor by a specified value or range of values. To ensure the difference in capacitance values meets the specified range, it is important to properly control the fabrication process of the ferroelectric capacitor. Since the capacitance value of a ferroelectric capacitor are dependent on process and/or temperature variations, the capacitance of a ferroelectric capacitor is determined by the process used to fabricate the FERAM. Therefore, the results of reading data from the 1T/1C FERAM are sensitive to process and temperature variations.
Accordingly, it would be advantageous to have a FERAM structure and a method for reading data from the FERAM structure which are reliable and insensitive to process and temperature variations. It is desirable for the FERAM structure to be simple and compact. It is also desirable that the process of reading data from the FERAM structure be fast and energy efficient.